System architecture for use with free space optical interconnects in a 3D stacked processor environment

J. Rorie; P. Marchand; P. Chandramani; J. Ekman; F. Kiamilev; F. Zane; V. Ozguz; S. C. Esener

System architecture for use with free space optical interconnects in a 3D stacked processor environment

J. Rorie, P. Marchand, P. Chandramani, J. Ekman, F. Kiamilev, F. Zane, V. Ozguz, S. C. Esener

Research output: Contribution to journal › Conference article › peer-review

Abstract

Stacking technology is an approach by which VLSI dies are stacked to form a three-dimensional logic unit. The free space optical interconnect is a technology suited for dealing with the unique constraints of three-dimensional stacked processors. The architecture supports the calculation of two dimensional fast Fourier transforms (FFT) and other signal processing functions using free space optical interconnects for communication between planes and stacks. Major architectural points are the development of reliable high-speed serial bus and an inter-processor communication protocol. This protocol must account for the unique requirements of the free space optical interconnects while maximizing the bandwidth available.

Original language	English (US)
Pages (from-to)	41-42
Number of pages	2
Journal	LEOS Summer Topical Meeting
State	Published - 1998
Externally published	Yes
Event	Proceedings of the 1998 IEEE/LEOS Summer Topical Meeting - Monterey, CA, USA Duration: Jul 20 1998 → Jul 24 1998

ASJC Scopus subject areas

Atomic and Molecular Physics, and Optics
Electrical and Electronic Engineering

Cite this

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abstract = "Stacking technology is an approach by which VLSI dies are stacked to form a three-dimensional logic unit. The free space optical interconnect is a technology suited for dealing with the unique constraints of three-dimensional stacked processors. The architecture supports the calculation of two dimensional fast Fourier transforms (FFT) and other signal processing functions using free space optical interconnects for communication between planes and stacks. Major architectural points are the development of reliable high-speed serial bus and an inter-processor communication protocol. This protocol must account for the unique requirements of the free space optical interconnects while maximizing the bandwidth available.",

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AU - Rorie, J.

AU - Marchand, P.

AU - Chandramani, P.

AU - Ekman, J.

AU - Kiamilev, F.

AU - Zane, F.

AU - Ozguz, V.

AU - Esener, S. C.

PY - 1998

Y1 - 1998

N2 - Stacking technology is an approach by which VLSI dies are stacked to form a three-dimensional logic unit. The free space optical interconnect is a technology suited for dealing with the unique constraints of three-dimensional stacked processors. The architecture supports the calculation of two dimensional fast Fourier transforms (FFT) and other signal processing functions using free space optical interconnects for communication between planes and stacks. Major architectural points are the development of reliable high-speed serial bus and an inter-processor communication protocol. This protocol must account for the unique requirements of the free space optical interconnects while maximizing the bandwidth available.

AB - Stacking technology is an approach by which VLSI dies are stacked to form a three-dimensional logic unit. The free space optical interconnect is a technology suited for dealing with the unique constraints of three-dimensional stacked processors. The architecture supports the calculation of two dimensional fast Fourier transforms (FFT) and other signal processing functions using free space optical interconnects for communication between planes and stacks. Major architectural points are the development of reliable high-speed serial bus and an inter-processor communication protocol. This protocol must account for the unique requirements of the free space optical interconnects while maximizing the bandwidth available.

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T2 - Proceedings of the 1998 IEEE/LEOS Summer Topical Meeting

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System architecture for use with free space optical interconnects in a 3D stacked processor environment

Abstract

ASJC Scopus subject areas

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